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Lattice Semiconductor
Figure 2. PCI Express Layers
Software
Transaction
Data Link
Physical
Logical Sub-block
Electrical Sub-block
Software
Transaction
Data Link
Physical
Logical Sub-block
Electrical Sub-block
PCI Express User’s Guide
Rx
Tx
Rx
Tx
Mechanical
Mechanical
Functional Description
The Lattice PCI Express core is an implementation of the logical sub-block of Physical layer, Data Link Layer and
part of the Transaction layer as speci?ed in the PCI Express Base speci?cation revision 1.0a.
? All con?guration registers are left out of the core and all required status signals are made available at the User
Interface side in order to facilitate an integrated easy implementation of con?guration registers in the User Logic.
? The Lattice PCI Express core does not currently support L0s, L1, L2 and External Loop back states
The following ?gure gives a graphical indication of the layers implemented (shaded blocks) in this PCI Express
solution (Lattice IP on ORT42G5 FPSC device).
Figure 3. PCI Express Layers Implemented
PCI
Express
PHY Layer
Electrical
sub block
PHY Layer
Logical sub
block
DATA LINK
Layer
Transaction Layer
and
Application Specific Logic
A typical implementation of these layers is better illustrated in the following block diagram.
4
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相关PDF资料
PCM18XH2 PROCESSOR MODULE MPLAB-ICE 2000
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PDA-B-24-615-E-2B1-1-C CIRCUIT BREAKER MAG 1P 15A
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